Calculators

Duty Cycle Calculator

Calculate PWM timing plus ideal average and RMS voltage.

Calculate PWM duty cycle, period, frequency, pulse width, and off-time from either frequency plus duty cycle or measured high and low pulse times.

Known values

Frequency

Duty cycle (%)

PWM voltage levels

Enter the ideal high and low levels to estimate average and RMS voltage over one cycle.

High level (V)Low level (V)

Duty cycle25%

Frequency1 kHz

Period1 ms

High time / pulse width250 µs

Low time750 µs

Ideal average voltage1.25 V

Ideal RMS voltage2.5 V

One-cycle timing diagram

25% duty cycle: high for 250 µs and low for 750 µs during each period.

This calculator describes an ideal repeating two-state waveform. It does not account for rise/fall time, jitter, dead time, modulation changes, hardware switching limits, load response, or filtering. Voltage results describe the entered ideal two-level waveform, not a guaranteed load voltage.

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About This Tool

Duty cycle describes what fraction of each repeating signal period is spent in the high or active state. It is commonly used with PWM motor control, LED dimming, switching converters, clocks, timers, and digital pulse measurements. This calculator works in both directions: enter frequency and duty cycle to find pulse width and low time, or use measured high/low times or pulse width/period to find duty cycle and frequency. Enter the waveform's high and low voltage levels to also estimate ideal average and RMS voltage. All calculations run locally in your browser.

How To Use It

Choose Frequency + duty cycle when you know the repetition frequency and percentage of each cycle that is high.
Choose High + low time when you measured the on-time and off-time, or Pulse width + period when you know the active pulse and complete cycle length.
Select the appropriate engineering unit. Frequency inputs support Hz, kHz, and MHz; pulse-time inputs support seconds through nanoseconds.
Read the calculated duty cycle, frequency, period, high time, and low time together, then use the one-cycle diagram to check how the high and low intervals fill the period.
Set the high and low voltage levels for an ideal two-level PWM waveform. Use average voltage for the waveform's DC component and RMS voltage for ideal resistive heating comparisons.

Examples

1 kHz PWM at 25% duty

A 1 kHz signal has a 1 ms period. At 25% duty cycle, it is high for 250 µs and low for 750 µs each cycle.

2 ms high and 6 ms low

The total period is 8 ms, so frequency is 125 Hz. The high state occupies 2/8 of the period, giving a 25% duty cycle.

250 µs pulse in a 1 ms period

A 250 µs pulse divided by a 1 ms total period gives 25% duty cycle, 750 µs low time, and 1 kHz frequency.

50% square-wave timing

At 50% duty cycle the ideal high and low times are equal. A 10 kHz signal therefore has a 100 µs period with 50 µs high and 50 µs low.

Useful Notes

Duty cycle formula

Duty cycle D = (t_high / T) × 100%, where t_high is the time spent high and T is the complete period. Because T = t_high + t_low, measured high and low times can directly determine the duty cycle.

Frequency and period

Frequency and period are reciprocals: f = 1/T and T = 1/f. A 1 kHz waveform repeats 1,000 times per second, so one ideal period lasts 1 ms.

Pulse width from PWM frequency

For a known frequency and duty cycle, high time is T × D/100 and low time is T minus high time. Pulse width often refers to this high-time interval, although terminology can vary by system.

Reading the timing diagram

The diagram shows one ideal period. The raised segment is the high or on-time, and the baseline segment is the low or off-time. Their widths follow the calculated duty-cycle percentage and always add up to one complete period.

0% and 100% duty cycle

The mathematical timing model permits 0% and 100%: the high time becomes zero at 0%, while the low time becomes zero at 100%. Some real PWM peripherals cannot generate these endpoints exactly or treat them as special constant-output states.

Real waveform limitations

Physical signals do not switch instantaneously. Rise time, fall time, jitter, propagation delay, dead time, minimum pulse width, timer resolution, and load behavior can make measured or usable timing differ from the ideal values.

Using the result

Use these results for timing checks and learning, then compare them with the timer, PWM peripheral, driver, switch, or load specifications when designing real hardware. A valid arithmetic duty cycle does not guarantee that a device can switch at the requested timing.

Average and RMS PWM voltage

For high level V_high, low level V_low, and duty fraction d, ideal average voltage is d × V_high + (1 − d) × V_low. RMS voltage is the square root of d × V_high² + (1 − d) × V_low². Average and RMS are different quantities: neither alone predicts a motor, LED, filtered converter, or reactive load without an appropriate circuit model.

FAQ

What does 25% duty cycle mean?

It means the signal is high for one quarter of each complete period and low for the remaining three quarters.

How do I calculate pulse width from frequency?

First find period with T = 1/f, then multiply the period by duty cycle divided by 100. For example, 1 kHz at 25% gives 1 ms × 0.25 = 250 µs.

Is duty cycle the same as frequency?

No. Frequency tells how often the waveform repeats; duty cycle tells what percentage of each repetition is spent high.

How are average and RMS PWM voltage calculated?

For the entered ideal high and low levels, average voltage is the time-weighted mean and RMS voltage is the square root of the time-weighted mean square. These waveform values do not by themselves predict delivered power or a real load's response; switching circuitry, filtering, and load behavior still matter.